Multi-bit counter

ABSTRACT

A multi-bit counter of the present invention is capable of high-speed operation because the time needed for increasing count values and combining count bits for a carry can be minimized by presetting all bit combinations for a unit having multiple bits and selecting the preset combinations by a clock signal, i.e., by presetting the state of each of the bit combinations and outputting a next required value.

BACKGROUND OF THE INVENTION

The present invention relates to a multi-bit counter, and, moreparticularly, to a multi-bit counter capable of executing high speedoperation by presetting all bit combinations for a unit having multiplebits and selecting the preset combinations by a clock signal.

FIG. 1 is a block diagram of a typical multi-bit counter, e.g., 6-bitcounter. As shown in FIG. 1, the 6-bit counter comprises unit countersCNT1 to CNT6 for detecting an initial input value applied via externaladdress signals EADD<0:5>. The external input can be set by a count setsignal CNTSET, and a count increase signal CNTINC increments the countin combination with a carry CAi to output internal address signalIADD<0:5>, and first to fourth carry generators 1-4, each for combiningthe carry CAi and the internal address signal IADDi of the correspondingunit counter, for applying the combined signal to the carry CA(i+1) ofthe next unit counter.

Each of the carry generators 1-4 includes a NAND gate ND forNAND-operating the carry CA(i−1) of the previous unit counter CNT(i−1)and the internal address signal IADD(i−1) of the previous unit counterCNT(i−1), and an inverter INV for inverting the output of the NAND gateND to output the carry CAi. Here, because a carry input port of thefirst unit counter CNT1 is coupled to a power voltage, the internaladdress signal IADD0 of the first unit counter is directly applied tothe carry CA1 of the second unit counter CNT2.

The unit counter CNTi as shown in FIG. 2, includes a NAND gate ND1 forNAND-operating the carry CA(i−1) of the previous unit counter CNT(i−1)and the counter increase signal CNTINC to output an inverted increasecontrol signal /INC; a first inverter INV1 for inverting the output ofthe NAND gate ND1 to an increase control signal INC; a second inverterINV2 for inverting the count set signal CNTSET; a third inverter INV3for inverting the external address signal EADDi; a first transfer gateTG1 for selectively transferring the output of the third inverter INV3under control of the count set signal CNTSET and the inverted count setsignal /CNTSET; fourth and fifth inverters INV4, INV5, the input of thefourth inverter coupled to the output of the fifth inverter and theinput of the fifth inverter coupled to the output of the fourth inverterlatching the signal selectively transferred through a first transfergate TG1; a sixth inverter INV6 for inverting the output signal of thefourth inverter INV4; seventh and eighth inverters INV7, INV8, the inputof the seventh inverter coupled to the output of the eighth inverter andthe input of the eighth inverter coupled to the output of the seventhinverter for latching the output signal of the sixth inverter INV6; anda second transfer gate TG2 for selectively transferring the signaltransferred selectively through the first transfer gate TG1 undercontrol of the increase control signal INC and the inverted increasecontrol signal /ICN, wherein the output signal of the seventh inverterINV7 and the signal selectively transferred through the second transfergate TG2 are coupled to generate the internal address signal IADDi.

Increase control signal INC is applied to the power ports of the fifthand sixth inverters INV5, INV6 and inverted increase control signal /INCis applied to the ground ports of the fifth and sixth inverters INV5,INV6. In addition, inverted increase control signal /INC is applied tothe power port of eighth inverter INV8 and increase control signal INCis applied to the ground port of eighth inverter IVN8.

The conventional multi-bit counter as described above outputs aninternal address signal and sets the internal state of each counter toprepare for generating the next internal address signal as directed by aclock signal. However, as the frequency of the clock signal increases,the margin of time required to compare and properly increase the outputof each bit counter in the multi-bit counter becomes insufficient, andthe frequency of the clock signal that can be used for the conventionalmulti-bit counter is restricted.

SUMMARY OF THE INVENTION

One aspect of the present invention provides a multi-bit counter capableof high-speed operation by presetting all bit combinations for a unithaving multiple bits and selecting the preset combinations by using aclock signal.

In accordance with an aspect of the present invention, there is provideda multi-bit counter comprising a multiplicity of unit counters, each forreceiving bit combinations of a unit external address signal, setting anexternal input by a count set signal and increasing bits by a countincrease signal and a carry to output an internal address signal and afinal state signal; and a plurality of logically combining means, eachfor combining the carry and the final state signal of each unit counter,for applying the combined signal to the carry of the next unit counter,the unit counter including: a NAND gate for NAND-operating the countincrease signal and a carry to output an increase control signal; afirst inverter for inverting the output of the NAND gate to output anincrease control signal; a multiplicity of state controlling units, eachreceiving the bit combinations of the unit external address signal tooutput a number of state signals; a multiplicity of state units forpresetting possible states for the bit combinations of the unit externaladdress signal by using the number of state signals from themultiplicity of state controlling units to selectively output the bitcombinations as a plurality of internal address signals; and second tofifth inverters, the input of the second inverter coupled to the outputof the third inverter and the input of the third inverter coupled to theoutput of the second inverter, the input of the fourth inverter coupledto the output of the fifth inverter and the input of the fifth invertercoupled to the output of the fourth inverter, for latching the pluralityof internal address signals selectively output by the number of stateunits.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects and features of the instant invention willbecome apparent from the following description of preferred embodimentstaken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram of a typical 6-bit counter;

FIG. 2 is a detailed circuit diagram of a unit counter in FIG. 1;

FIG. 3 is a block diagram of a multi-bit counter in accordance with thepresent invention;

FIG. 4 is a detailed circuit diagram of a first embodiment of a unitcounter in FIG. 3;

FIG. 5 is a detailed circuit diagram of a second embodiment of the unitcounter in FIG. 3;

FIG. 6 is a detailed circuit diagram of a carry adder for generating apropagating signal in FIG. 5;

FIG. 7 is a timing diagram for operation of the block diagram in FIG. 3;and

FIG. 8 is a block diagram of another embodiment of the multi-bit counterin accordance with the present invention.

DESCRIPTION OF THE SPECIFIC EMBODIMENTS

Preferred embodiments of the present invention will now be described indetail with reference to the accompanying drawings.

FIG. 3 is a block diagram of a multi-bit counter of the presentinvention, which is an 8-bit counter having two bit sets as an example.As shown in FIG. 3, the multi-bit counter comprises first to fourth unitcounters CNT11-CNT14 for detecting an initial input value by externaladdress signals EADD<0:7>, setting an external input by a count setsignal CNTSET and increasing a count increase signal CNTINC and a carryCAi to generate internal address signal IADD<0:7> and final statesignals STn; and first and second carry generators 11, 12 for combiningthe carry of the unit counters CAi and final state signal ST3 to applythe combined signal to carry CA (i+1) of the next unit counter.

Each of the carry generators 11, 12 includes a NAND gate ND11 forNAND-operating the carry CA(i−1) of the previous unit counter CNT(i−1)and final state signal ST3, and an inverter INV11 for inverting theoutput of NAND gate ND11 to output the carry CAi. Here, because thecarry input port of first unit counter CNT11 is coupled to a powervoltage, final state signal ST3 is directly applied to carry CA2 ofsecond unit counter CNT12.

FIG. 4 provides a detailed circuit diagram of a first embodiment of afirst unit counter CNT11, which includes a NAND gate ND21 forNAND-operating the count increase signal CNTINC and the carry (becausefirst counter CNT11 is shown, the carry is power voltage level VCC) tooutput an inverted increase control signal /INC; a first inverter IVN21for inverting the output signal of NAND gate ND21 to output an increasecontrol signal INC; first to fourth state control units STCON1-STCON4for receiving the combination of first and second external addresssignals EADD0, EADD1 to output first to fourth state signals ST0-ST3;first to fourth state units STU1-STU4 for presetting all bitcombinations for a unit constructed by two count bits of first to fourthstate signals ST0-ST3 of first to fourth state control unitsSTCON1-STCON4 and selectively outputting each combination as first andsecond internal address signals IADD0, IADD1 second and third invertersIVN22, INV23, the input of the second inverter coupled to the output ofthe third inverter and the input of the third inverter coupled to theoutput of the second inverter, for latching first and second internaladdress signals IADD0, IADD1 selectively output by first to fourth stateunits STU1-STU4; and fourth and fifth inverters INV24, INV25, the inputof the fourth inverter, for latching first and second internal addresssignals IADD0, IADD1 selectively output by first to fourth state unitsSTU1-STU4.

Output signal OUT4 of fourth state control unit STCON4 is fed back to aninput of first state control unit STCON1.

First state control unit STCON1 includes a NAND gate ND31 forNAND-operating inverted first external address signal /EADD0 andinverted second external address signal /EADD1; a first inverter INV31for inverting the output signal of NAND gate ND31; a first transfer gateTG21 for selectively transferring the output signal of first inverterINV31 under control of count set signal CNTSET and inverted count setsignal /CNTSET; second and third inverters INV32, INV33, the input ofthe second inverter coupled to the output of the third inverter and theinput of the third inverter coupled to the output of the secondinverter, for latching the signal selectively transferred through firsttransfer gate TG21, a second transfer gate TG22 for selectivelytransferring the output signal of second inverter INV32 under control ofincrease control signal INC and inverted increase control signal /INC;fourth and fifth inverters INV34, INV35, the input of the fourthinverter coupled to the output of the fifth inverter and the input ofthe fifth inverter coupled to the output of the fourth inverter, forlatching the signal selectively transferred through second transfer gateTG22 to output first state signal ST0; a sixth inverter INV36 forinverting first state signal ST0 to output inverted state signal /ST0;and a third transfer gate TG23 for selectively transferring the outputsignal of fourth inverter INV34 under control of inverted increasecontrol signal /INC and increase control signal INC to output an outputsignal OUT1.

First state unit STU1 includes first and second transfer gates TG31,TG32 for selectively transferring the ground voltage VSS under controlof inverted first state signal /ST0 and first state signal ST0, andsecond state unit STU2 includes third and fourth transfer gates TG33,TG34 for selectively transferring, respectively, ground voltage VSS andpower voltage VCC under control of inverted second state signal /ST1 andsecond state signal ST1. Third state unit STU3 includes fifth and sixthtransfer gates TG35, TG36 for selectively transferring, respectively,power voltage VCC and ground voltage VSS under control of inverted thirdstate signal /ST2 and third state signal ST2; and fourth state unit STU4includes seventh and eighth transfer gates TG37, TG38 for selectivelytransferring power voltage VCC under control of inverted fourth statesignal /ST3 and fourth state signal ST3.

FIG. 5 represents a detailed circuit diagram of a second embodiment ofthe first unit counter CNT11, which includes a set control unit 10having a first NAND gate ND41 for NAND-operating a propagating signalNEXTi and count set signal CNTSET to output an inverted first set signal/SET1; a first inverter 1NV41 for inverting the output of first NANDgate ND41 to output a first set signal SET1; a second inverter INV42 forinverting the propagating signal NEXTi; a second NAND gate ND42 forNAND-operating the output of second inverter INV42 and count set signalCNTSET to output an inverted second set signal /SET2; and a thirdinverter INV43 for inverting the output of second NAND gate ND42 tooutput a second set signal SET2; an increase control unit 20 having athird NAND gate ND43 for NAND-operating the CAi and count increasesignal CNTINC to output an inverted increase control signal /INC; and afourth inverter INV44 for inverting the output of third NAND gate ND43to output an increase control signal INC; first to fourth state controlunits STCON1-STCON4 receiving a combination of first and second externaladdress signals EADD0, EADD1 to output first to fourth state signalsST0-ST3; first to fourth state units STU1-STU4 for presetting all bitcombinations for a unit constructed by two count bits of first to fourthstate control units STCON1-STCON4 and for selectively outputting eachcombination as internal address signals IADD0, IADD1; fifth and sixthinverters INV45, INV46, and seventh and eighth inverters INV47, INV48,the input of the fifth inverter coupled to the output of the sixthinverter and the input of the sixth inverter coupled to the output ofthe fifth inverter, the input of the seventh inverter coupled to theoutput of the eighth inverter and the input of the eighth invertercoupled to the output of the seventh inverter, for latching first andthe second internal address signals IADD0, IADD1 selectively output byfirst to fourth state units STU1-STU4.

Output signal OUT14 of the fourth state control unit STCON4 is fed backto an input of first state control unit STCON1.

First state control unit STCON1 includes a NAND gate ND51 forNAND-operating inverted first external address signal /EADD0 andinverted second external address signal /EADD1; a first inverter INV51for inverting the output of NAND gate ND51; a first transfer gate TG41for selectively transferring the output signal of first inverter INV51under control of the inverted second set signal /SET2 and the second setsignal SET2; second and third inverters INV52, INV53, the input of thesecond inverter coupled to the output of the third inverter and theinput of the third inverter coupled to the output of the secondinverter, for latching the signal selectively transferred through firsttransfer gate TG41; a second transfer gate TG42 for selectivelytransferring the output of second inverter INV52 under control ofinverted increase control signal /INC; fourth and fifth inverters INV54,INV55, the input of the fourth inverter coupled to the output of thefifth inverter and the input of the fifth inverter coupled to the outputof the fourth inverter, for latching the signal selectively transferredthrough second transfer gate TG42; a sixth inverter INV56 for invertingthe output signal of fourth inverter INV54 to output inverted firststate signal /ST0; a third transfer gate TG43 for selectivelytransferring the output of fourth inverter INV54 under control ofinverted increase control signal /INC and increase control signal INC tooutput the output signal OUT11; and a fourth transfer gate TG44 forselectively transferring the output of first inverter INV51 undercontrol of inverted first set signal /SET1 and first set signal SET1.

The configuration for second to the fourth state control unitsSTCON2-STCON4 is similar to that of first state control unit STCON1, inwhich the signal transferred through fourth transfer gate TG44 of theprevious state and output signal OUT11 of the previous stage areapplied.

First state unit STU1 includes first and second transfer gates TG51,TG52 for selectively transferring ground voltage VSS under control ofinverted first state signal /ST0 and first state signal ST0,respectively, and second state unit STU2 includes third and fourthtransfer gates TG53, TG54 for selectively transferring ground voltageVSS and power voltage VCC under control of inverted second state signal/ST1 and second state signal ST1, respectively. Third state unit STU3includes fifth and sixth transfer gates TG55, TG56 for selectivelytransferring power voltage VCC and ground voltage VSS under control ofinverted third state signal /ST2 and third state signal ST2,respectively; and fourth state unit STU4 includes seventh and eighthtransfer gates TG57, TG58 for selectively transferring power voltage VCCunder control of inverted fourth state signal /ST3 and fourther statesignal ST3, respectively.

FIG. 6 is a detailed circuit diagram of a carry adder 30 for generatinga propagating signal NEXTi, which includes a first NAND gate ND61 forNAND-operating first and second external address signals EADD0, EADD1; afirst inverter INV61 for inverting the output of first NAND gate ND61 tooutput a first propagating signal NEXT1; a second NAND gate ND62 forNAND-operating third and fourth external address signals EADD2, EADD3; asecond inverter INV62 for inverting the output of second NAND gate ND62to output a second propagating signal NEXT2; a third NAND gate ND63 forNAND-operating first and second propagating signals NEXT1, NEXT2; athird inverter INV63 for inverting the output signal of third NAND gateND63; a fourth NAND gate ND64 for NAND-operating the output of thirdinverter INV63 and fifth and sixth external address signals EADD4,EADD5; a fourth inverter INV64 for inverting the output of fourth NANDgate ND64 to output a third propagating signal NEXT3; a fifth NAND gateND65 for NAND-operating first to third propagating signals NEXT1-NEXT3;a fifth inverter INV65 for inverting the output of fifth NAND gate ND65;a sixth NAND gate ND66 for NAND-operating the output of fifth inverterINV65 and seventh and eighth external address signals EADD6, EADD7; anda sixth inverter INV66 for inverting the output of sixth NAND gate ND66to output a fourth propagating signal NEXT4.

In the 8-bit counter of the present invention as described above, allbit combinations for the unit are made up of two or more bits. The bitsare preset and each combination is controlled to be selected. Therefore,the present invention is capable of high-speed operation because thetime needed to increase the count value and to add the carry from eachcounter bit can be minimized.

First, the external address value is input to detect the initial inputvalue to the input of the counter. Then the count set signal CNTSET forsetting the external input and the count increase signal CNTINC forincreasing each counter bit are input. At that time, the carry of alower bit set is also input except for the lowest bit set.

In the embodiment described above, each of the state units STU1-STU4 isconstructed using a typical 4 bit shift register, as an example, inwhich only one bit is made high (or low) by an initial count set signalCNTSET. The register to be set high is determined by the externaladdress signal. Alternatively, the register can be set to output a valuethat is one step higher than the external address signal.

FIG. 7 is a simulation result for the operation of the multi-bit counterof the present invention, where the clock signal frequency is set at 333MHz.

FIG. 8 is a block diagram of another embodiment of the multi-bit counterin accordance with the present invention, where carry generators 21, 22are different from other embodiments of the multi-bit counter asdescribed above.

In this embodiment, each of the carry generators 21, 22 includes a ANDgate ND71 for NAND-operating the final state signals of all unitcounters and an inverter INV71 for inverting the output of NAND gateND71 to generate the carry CAi.

The operation of the embodiment of the multi-bit counter of the presentinvention shown in FIG. 8 is similar to that of the other embodiments.

As described above, the present invention is capable of high-speedoperation by presetting all bit combinations for the unit constructed bymultiple bits and selecting each preset combination.

While the present invention has been shown and described with respect tothe particular embodiments, it will be apparent to those skilled in theart that many changes and modifications may be made without departingfrom the spirit and scope of the invention as defined in the appendedclaims.

What is claimed is:
 1. A multi-bit counter comprising a multiplicity ofunit counters, each for receiving bit combinations of a unit externaladdress signal, setting an external input by a count set signal andincreasing bits by a count increase signal and a carry to output aninternal address signal and a final state signal; and a plurality oflogical combining means, each for combining the carry and the finalstate signal of each unit counter to apply the combined signal to thecarry of a next unit counter, the unit counter including: a first NANDgate for NAND-operating the count increase signal and the carry tooutput an inverted increase control signal; a first inverter forinverting the output of the first NAND gate to output an increasecontrol signal; a multiplicity of counting means, each receiving the bitcombinations of the unit external address signal to output a number ofstate signals; a multiplicity of state means for presetting all possiblebit combinations of the unit external address signal and selectivelyoutputting bit combinations as a plurality of internal address signalsin response to the state signals outputted from the multiplicity ofcounting means; and a second to a fifth inverter, an input of the secondinverter coupled to an output of the third inverter and an input of thethird inverter coupled to an output of the second inverter, an input ofthe fourth inverter coupled to an output of the fifth inverter and aninput of the fifth inverter coupled to an output of the fourth inverter,for latching the plurality of the internal address signals selectivelyoutputted by the multiplicity of the state means.
 2. The multi-bitcounter of claim 1, wherein each of the counting meanscomprises: asecond NAND gate for NAND-operating the inverted unit external addresssignal; a sixth inverter for inverting the output of the second NANDgate; a first transfer gate for selectively transferring the output ofthe sixth inverter under control of the count set signal and an invertedcount set signal; a seventh and an eighth inverter, the input of theseventh inverter coupled to the output of the eighth inverter and theinput of the eighth inverter coupled to the output of the seventhinverter, for latching the signal selectively transferred through thefirst transfer gate; a second transfer gate for selectively transferringthe output of the seventh inverter under control of the, increasecontrol signal and the inverted increase control signal; a ninth and atenth inverter, the input of the ninth inverter coupled to the output,of the tenth inverter and the input of the tenth inverter coupled to theoutput of the ninth inverter forlatching the signal selectivelytransferred through the second transfer gate to the output the statesignal; an eleventh inverter for inverting the state signal to and athird transfer gate for selectively transferring the output signal ofthe ninth inverter under control of the inverted increase control signaland the increase control signal to output an output signal, wherein anoutput signal of the last one of the counting means is fed back to aninput of the first one of the counting means.
 3. The multi-bit counterof claim 1, wherein each of the state means includes a number oftransfer gates for selectively transferring the combined state undercontrol of the inverted state signal and the state signal.
 4. Themulti-bit counter of claim 1, further including carry generating meanscomprising: a second NAND gate for NAND-operating the carry of theprevious unit counter and the final state signal; and a sixth inverterfor inverting the output of the second NAND gate to output the carry,wherein the carry input port of the first unit counter is coupled to apower voltage so that the final state signal of the first unit counteris directly applied to the carry of the next unit counter.
 5. Amulti-bit counter comprising a multiplicity of unit counters, each forreceiving bit combinations of a unit external address signal, setting anexternal input by a count set signal and increasing bits by a countincrease signal and a carry to output an internal address signal and afinal state signal; and a plurality of logical combining means, each forcombining the carry and the final state signal of each unit counter toapply the combined signal to the carry of a next unit counter, the unitcounter including: set controlling means receiving a plurality ofpropagating signals and a count set signal to output a multiplicity ofset signals; increasing controlling means receiving a carry of aprevious stage and a count increase signal to output a number ofincrease control signal; a multiplicity of counting means, eachreceiving the bit combinations of the unit external address signal tooutput a number of state signals; a multiplicity of state means forpresetting all possible bit combinations of the unit external addresssignal and selectively outputting bit combinations as a plurality ofinternal address signals in response to the state signals outputted fromthe multiplicity of counting means; and a second to a fifth inverter, aninput of the second inverter coupled to an output of the third inverterand an input of the third inverter coupled to an output of the secondinverter, an input of the fourth inverter coupled to an output of thefifth inverter and an input of the fifth inverter coupled to an outputof the fourth inverter, for latching the plurality of the internaladdress signals selectively outputted by the multiplicity of the statemeans.
 6. The multi-bit counter of claim 5, wherein each of the countingmeans comprises: a NAND gate for NAND-operating the inverted unitexternal address signal; a sixth inverter for inverting the output ofthe NAND gate; a first transfer gate for selectively transferring theoutput of the sixth inverter under control of an inverted second setsignal and the second set signal; a seventh and an eighth inverter, theinput of the seventh inverter coupled to the output of the eighthinverter and the input of the eighth inverter coupled to the output ofthe seventh inverter, for latching the signal selectively transferredthrough the first transfer gate; a second transfer gate for selectivelytransferring the output of the seventh inverter under control of theincrease control signal and an inverted increase control signal; a ninthand a tenth inverter, the input of the ninth inverter coupled to theoutput of the tenth inverter and the input of the tenth inverter coupledto the output of the ninth inverter, for latching the signal selectivelytransferred through the second transfer gate to output the first statesignal; an eleventh inverter for inverting the output of the ninthinverter to output an inverted first state signal; a third transfer gatefor selectively transferring the output signal of the fourth inverterunder control of the inverted increase control signal and the increasecontrol signal to output an output signal; and a forth transfer gate forselectively transferring the output of the first inverter under controlof an inverted first set signal and the first set signal; wherein thesignal selectively transferred through the fourth transfer gate of theprevious stage and the output signal of the previous stage are applied,and the output signal of the last one of the counting means is fed backto an input of the first one of the counting means.
 7. The multi-bitcounter as recited in claim 5, wherein each of the state means comprisesa number of transfer gates for selectively transferring the combinedstates, under control of the inverted state signal and the state signal.8. The multi-bit counter as recited in claim 5, further including carrygenerating means comprising: a NAND gate for NAND-operating the carryand the final state signal of the previous unit counter; and a sixthinverter for inverting the output of the NAND gate to output the carry,wherein the carry input port of the first unit counter is coupled to apower voltage so that the final state signal of the first unit counteris directly applied to the carry of the next unit counter.
 9. Themulti-bit counter as recited in claim 5, wherein one of the propagatingsignals is output from a carry adding means, the carry adding meanscomprising: a first NAND gate for NAND-operating a first and a secondexternal address signal; a sixth inverter for inverting the output ofthe first NAND gate to output a first propagating signal; a second NANDgate for NAND-operating a third and a fourth external address signal; aseventh inverter for inverting the output of the second NAND gate tooutput a second propagating signal; a third NAND gate for NAND-operatingthe first and second propagating signals; an eighth inverter forinverting the output of the third NAND gate; a fourth NAND gate forNAND-operating the output of the eighth inverter and a fifth and a sixthexternal address signal; a ninth inverter for inverting the output ofthe fourth NAND gate to output a third propagating signal; a fifth NANDgate for NAND-operating the first to the third propagating signals; atenth inverter for inverting the output of the fifth NAND gate; a sixthNAND gate for NAND-operating the output of the tenth inverter andseventh and eighth external address signals; and an eleventh inverterfor inverting the output of the sixth NAND gate to output a fourthpropagating signal.
 10. The multi-bit counter as recited in claim 5,wherein the set controlling means comprises: a first NAND gate forNAND-operating the propagating signals and the count set signal tooutput an inverted first set signal; a sixth inverter for inverting theoutput of the first NAND gate to the first set signal; a seventhinverter for inverting the plurality of propagating signals; a secondNAND gate for NAND-operating the output of the seventh inverter and thecount set signal to output the second set signal; and a eighth inverterfor inverting the output of the second NAND gate to output the secondset signal.
 11. The multi-bit counter as recited in claim 5, wherein theincrease controlling means includes: a NAND gate for NAND-operating thecount increase signal and the carry to output the inverted increasecontrol signal; and a sixth inverter for inverting the output signal ofthe NAND gate to output the increase control signal.
 12. A multi-bitcounter having a plurality of counter units, the multi-bit countercomprising: a first counter unit having a first input for receiving afirst external address signal, a second input for receiving a secondexternal address signal, a third input for receiving a count set signal,a fourth input for receiving a count increase signal and a fifth inputfor receiving a carry signal, a first output for providing a firstinternal address signal, a second output for providing a second internaladdress signal and a third output for providing a first final statesignal; a carry generator circuit having a first input for receiving thefirst final state signal of the first unit counter, a second inputcoupled to the fifth input of the first counter unit, an output forproviding a combined carry signal; and a second counter unit having afirst input for receiving a third external address signal, a secondinput for receiving a fourth external address signal, a third input forreceiving the count set signal, a fourth input for receiving the countincrease signal, a fifth input for receiving the combined carry signalfrom the carry generator circuit, a first output for providing a thirdinternal address signal, a second output for a fourth internal addresssignal and a third output for providing a second final state signal. 13.The multi-bit counter of claim 12 wherein, the first counter unitcomprises: a first logic gate for receiving the count increase signaland the carry signal to output an inverted increase control signal; anda first inverter for inverting the output of the first logic gate tooutput an increase control signal.
 14. The multi-bit counter of claim 13wherein, the first counter unit further comprises: at least one statecontrol unit for receiving one or more external address signals toprovide one or more state signal outputs.
 15. The multi-bit counter ofclaim 14 wherein, the first counter unit further comprises: at least onestate unit for presetting all possible bit combinations of the externaladdress signal and selectively outputting bit combinations of aninternal address signal.
 16. The multi-bit counter of claim 15 wherein,the first counter unit further comprises: a second inverter; and a thirdinverter, wherein the second inverter has an input coupled to an outputof the third inverter, wherein the third inverter has an input coupledto an output of the second inverter, wherein the input of the secondinverter is for receiving one or more internal address signals.
 17. Themulti-bit counter of claim 16 wherein, the first counter unit furthercomprises: a fourth inverter; and a fifth inverter, wherein the fourthinverter has an input coupled to an output of the fifth inverter,wherein the fifth inverter has an input coupled to an output of thefourth inverter, and wherein the input of the fourth inverter is forreceiving one or more internal address signals.
 18. A counter circuitcomprising: a first logic circuit for receiving a count increase signaland a carry signal to output an increase control signal and an invertedincrease control signal; a state control unit for receiving a count setsignal, a first external address signal and a second address signal tooutput a state signal and an inverted state signal, wherein the countset signal, the increase control signal and the inverted increasecontrol signal are configured to selectively output the state signal andthe inverted state signal; and a state unit for presetting all possiblebit combinations of the first external address signal and the secondexternal address signal to selectively output bit combinations of afirst internal address signal and a second internal address signal,wherein the state signal and the inverted state signal are configured toselectively output said bit combinations of the internal addresssignals.
 19. The counter circuit of claim 18, wherein the first logiccircuit comprises: a logic gate for receiving the count increase signaland the carry signal to output an inverted increase control signal; anda first inverter for inverting the output of the logic gate to outputthe increase control signal.
 20. The counter circuit of claim 19 furthercomprising: a second logic circuit comprising a second inverter; and athird inverter, wherein the second inverter has an input coupled to anoutput of the third inverter, wherein the third inverter has an inputcoupled to an output of the second inverter, wherein the input of thesecond inverter is for receiving one or more internal address signals.21. The counter circuit of claim 20 further comprising: a third logiccircuit comprising a fourth inverter; and a fifth inverter, wherein thefourth inverter has an input coupled to an output of the fifth inverter,wherein the fifth inverter has an input coupled to an output of thefourth inverter, wherein the input of the fifth inverter is forreceiving at least one internal address signal.
 22. The counter circuitof claim 18, wherein the state control unit comprises: a logic gate forreceiving an inverted first external address signal and an invertedsecond external address signal to provide an output signal; a firstinverter for inverting said output signal of the logic gate; a firsttransfer gate for selectively transferring an output signal of the firstinverter under control of a count set signal and an inverted count setsignal; a second inverter having an input coupled to an output of athird inverter, wherein an input of the third inverter is coupled to anoutput of the second inverter for latching the signal selectivelytransferred through the first transfer gate; a second transfer gate forselectively transferring the output signal of second inverter undercontrol of the increase control signal and inverted increase controlsignal; a fourth inverter having an input coupled to the output of afifth inverter, wherein an input of the fifth inverter is coupled to anoutput of the fourth inverter, for latching a signal selectivelytransferred through the second transfer gate to output the state signal;a sixth inverter for inverting the state signal to output the invertedstate signal; and a third transfer gate for selectively transferring anoutput signal of the fourth inverter under control of the invertedincrease control signal and the increase control signal to provide anoutput signal.
 23. The counter circuit of claim 18, wherein the stateunit comprises: a first transfer gate; and a second transfer gate,wherein the transfer gates are for selectively transferring a groundvoltage under control of the state signal and the inverted state signal.24. A multi-bit counter comprising a multiplicity of unit counters, eachfor receiving bit combinations of a unit external address signal,setting an external input by a count set signal and increasing bits by acount increase signal and a carry to output an internal address signaland a final state signal, and a plurality of logical circuits, each forcombining the carry and the final state signal of each unit counter toapply the combined signal to a carry of a next unit counter, the unitcounter including: a logic gate for receiving the count increase signaland the carry to output an inverted increase control signal; a firstinverter for inverting the output of the logic gate to output anincrease control signal; a plurality of state control units, eachreceiving the bit combinations of the unit external address signal tooutput a number of state signals; a plurality of state units forpresetting all possible bit combinations of the unit external addresssignal and selectively outputting bit combinations as a plurality ofinternal address signals in response to the state signals outputted fromthe plurality of state control units; and a second to a fifth inverter,an input of the second inverter coupled to an output of the thirdinverter and an input of the third inverter coupled to an output of thesecond inverter, an input of the fourth inverter coupled to an output ofthe fifth inverter and an input of the fifth inverter coupled to anoutput of the fourth inverter, for latching the plurality of theinternal address signals selectively outputted by the plurality of thestate units.
 25. A multi-bit counter comprising a plurality of unitcounters, each for receiving bit combinations of a unit external addresssignal, setting an external input by a count set signal and increasingbits by a count increase signal and a carry to output an internaladdress signal and a final state signal, and a plurality of logicalcircuits, each for combining the carry and the final state signal ofeach unit counter to apply the combined signal to a carry of a next unitcounter, the unit counter including: a set controlling unit receiving aplurality of propagating signals and a count set signal to output amultiplicity of set signals; an increase control unit receiving a carryof a previous stage and a count increase signal to output an increasecontrol signal; a plurality of state control units, each receiving thebit combinations of the unit external address signal to output a numberof state signals; a plurality of state units for presetting all possiblebit combinations of the unit external address signal and selectivelyoutputting bit combinations as a plurality of internal address signalsin response to the state signals outputted from the plurality of statecontrol units; and a second to a fifth inverter, an input of the secondinverter coupled to an output of the third inverter and an input of thethird inverter coupled to an output of the second inverter, an input ofthe fourth inverter coupled to an output of the fifth inverter and aninput of the fifth inverter coupled to an output of the fourth inverter,for latching the plurality of the internal address signals selectivelyoutputted by the multiplicity of the state units.
 26. A counter circuitcomprising: a first logic circuit for receiving at least one propagatingsignal and a count set signal to output a one or more set signals; asecond logic circuit for receiving a carry signal and a count increasesignal to output an increase control signal; a state control unit forreceiving a first external address signal and a second external addresssignal to output a state signal and an inverted state signal, whereinthe set signal, the increase control signal and the inverted increasecontrol signal are configured to selectively output the state signal andthe inverted state signal; and a state unit for presetting all possiblebit combinations of the first external address signal and the secondexternal address signal to selectively output bit combinations of afirst internal address signal and a second internal address signal,wherein the state signal and the inverted state signal are configured toselectively output said bit combinations of the internal addresssignals.
 27. The counter circuit of claim 26 further comprising: a firstto a fourth inverter, an input of the first inverter coupled to anoutput of the second inverter and an input of the second invertercoupled to an output of the first inverter, an input of the thirdinverter coupled to an output of the fourth inverter and an input of thefourth inverter coupled to an output of the third inverter, for latchingsaid bit combinations of the internal address signals.